1. Field of the Invention
The present invention relates to a hybrid memory device provided with a memory cell to store binary data as a polarization state of a ferroelectric layer and a method for manufacturing the same.
2. Description of Related Arts
Ferroelectric Random Access Memory (hereinafter referred to as FeRAM) is a representative form of ferroelectric memory.
Recently, as so-called SOC (system on chip) technology has been developed, a hybrid memory device having a structure provided with functions different from those of FeRAM cells, i.e., integrating a logic circuit to perform processes related to the FeRAM cells and an RF circuit or the like into one chip, has been introduced (see pages 112-125 of NEW DEVELOPMENT OF FeRAM, CMC Publication).
A ferroelectric layer incorporated into the above-described FeRAM is formed of an oxygen compound material. The oxygen compound material is reduced by hydrogen (H2) generated from moisture (H2O) formed around the ferroelectric layer, e.g., unavoidably penetrated into a CVD (chemical mechanical deposition) layer. This reduction reaction leads to deterioration in the polarization characteristics of the ferroelectric layer.
For example, a structure having a hydrogen diffusion barrier layer made of aluminum oxide is disclosed in Japanese Patent Laid-Open No. 2002-43541, wherein the hydrogen diffusion barrier layer is formed on a metal wiring layer connected to the ferroelectric layer for the purpose of preventing the hydrogen generated during a passivation process from diffusing into the ferroelectric layer.
In addition, a structure having a moisture diffusion barrier layer made of Si3N4 covering a top surface and sides of a metal wiring for the purpose of reducing an influence of the hydrogen generated during the formation of a passivation layer is disclosed in Japanese Patent Laid-Open No. 2003-100994.
Using the above-mentioned structures of the Japanese Patents Laid-Open Nos. 2002-43541 and 2003-1009943 the hydrogen (or moisture) diffusion barrier layer made of aluminum oxide or Si3N4 is directly formed on the metal wiring.
Formation of these barrier layers leads to so-called charge up phenomena, wherein a charge is formed on the metal wiring.
Hereinafter, an additional example of a conventional ferroelectric memory provided with a structure to prevent charge-up is described with reference to the drawings.
FIG. 1 A is an explanatory diagram of the prior art as viewed from the top of a conventional FeRAM. FIG. 1B is an explanatory diagram of the prior art showing a cross-section formed by cutting a plane along the dash dotted line B-B′ of FIG. 1A.
The ferroelectric memory 100 is provided with a semiconductor substrate 111. The semiconductor substrate 111 is divided into a memory cell array region 101 and a logic circuit region 102 encompassing the memory cell array region 101.
A memory cell device 110 is formed in the memory cell array region 101. And, a logic circuit device 120 is formed in the logic circuit region 102. These memory cell device 110 and logic circuit device 120 are separated by a field oxide layer 103 formed, for example, by a LOCOS (local oxidation of silicon) method.
The memory cell device 110 is, for example, a device such as a transistor. The memory cell device 110 has, for example, a memory cell diffusion region 112, a memory cell gate insulating layer 114 and a memory cell gate electrode 116 formed on the memory cell gate insulating layer 114 as constituent elements of the transistor.
The logic circuit device 120 is, similar to the memory cell device 110, a device such as a transistor. The logic circuit device 120 has, for example, a logic circuit device diffusion region 122, a logic circuit device gate insulating layer 124 and a logic circuit device gate electrode 126 formed on a logic circuit insulating layer 124 as constituent elements of the transistor.
A first insulating layer 130 is formed in the memory cell array region 101 formed thereon the memory cell device 110 and the logic circuit region 102 formed thereon the logic circuit device 120.
A ferroelectric capacitor structure 140 is disposed on the partial region in the memory cell array region 101 as a region of the first insulating layer 130 is disposed. The ferroelectric capacitor structure 140 has a structure obtained by stacking a bottom electrode 142, a ferroelectric layer 144 and a top electrode 146 in the named order from the side of the semiconductor substrate 111.
The second insulating layer 150 is formed by covering a top surface of the first insulating layer 130 including the ferroelectric capacitor structure 140. Therefore, the second insulating layer is formed over the memory cell region 101 and the logic circuit region 102.
On a surface 150a of the second insulating layer 150, memory cell contact holes 162 extend from a surface portion in the memory cell array region 101 to the ferroelectric capacitor structure 140 is formed. The memory cell contact holes 162 are formed into buried contacts 163 by filling them with a conductive material. Similarly, the memory cell contact holes 162 are formed from the surface 150a of the second insulating layer 150 to the memory cell diffusion region 112 of the memory cell device 110. The memory cell contact holes 162 are formed into the buried contacts 163 by filling them with a conductive material.
In addition, in the surface 150a of the second insulating layer 150, the logic contact holes 166, extending from the surface portion in the logic circuit region 102 to the logic circuit device 120, are formed. The logic circuit contact holes 166 are formed into the logic circuit buried contacts 167 by filling them with a conductive material.
The first wiring unit 172 extends to the partial region in the memory cell array region 101 among the second insulating layer 150. The first wiring unit 172 is electrically connected to the buried contacts 163.
The second wiring unit 174 extends to the partial region in the logic circuit region 102 among the second insulating layer 150. The second wiring unit 174 is electrically connected to the logic circuit buried contact 167. These first and second wiring units 172 and 174 are formed in the same plane as the second insulating layer 150, i.e., the surface 150a, as the wiring layer 170.
The liner oxide layer 180 is disposed so as to cover the memory cell array region 101 and the logic circuit region 102. The liner oxide layer 180 is made of, for example, silicon oxide or NSG (Non-doped Silicate Glass) (hereinafter simply referred to as a P-TEOS layer) formed using TEOS (Tetraethoxysilane) applied by plasma CVD (Chemical Vapor Deposition).
A cover layer 190 is formed on the liner oxide layer 180. The cover layer 190 is, for example, a thin layer of an alumina (Al2O3).
As previously described above, if the hydrogen (or moisture) diffusion barrier layer is directly formed on the metal wiring, charge up phenomena occur in the metal line. It is possible for this to result in breakdown of the gate oxide layer of the electrically connected transistor through the buried contacts connected to the metal wiring or the like.
That is, if the gate oxide layer becomes like that, for example, the function of the logic circuit device such as memory cell control is broken; and further; the ferroelectric memory malfunctions.
In general, the surface area of the metal wiring formed on the logic circuit region, excluding the memory cell array region, is greater than the surface area (sum of the top surface and side are˜) of the first metal wiring (the first wiring layer) formed on the memory cell array region. Therefore, particularly, the breakdown of the gate insulating layer of the transistor due to the charge-up phenomena occurs easily in the logic circuit region.
In the example shown in the drawings, the liner oxide layer is formed in order to prevent such charge-up phenomena before the formation of the cover layer. The liner oxide layer is formed, e.g., by the CVD method, as previously described above.
As described above, moisture is unavoidably trapped in the layer formed by the CVD method. Furthermore, this moisture is dissolved by the heat process, thereby occasionally being converted into hydrogen.
As a result, an annealing process, conducted at a temperature of about 700° C., is essential to prevent the ferroelectric layer from being exposed to any one or both of the moisture and the hydrogen and for the purpose of dehydration and/or dehydrogenation in a prior art.
However, if the annealing process is performed under these conditions, particularly, the electrical characteristics of the transistor formed on a region except for the memory cell array region, i.e., for this example, the logic circuit region, may be changed. In addition, there is a problem that the characteristics of ferroelectric layer are deteriorated.